A growing number of electrical devices, which may be ICs or embedded cores within ICs, are being tested using test compression architectures (TCA), such as Mentor's TestKompress™ embedded deterministic test technology, incorporated herein by reference. Fundamentally a TCA consists of three elements, a decompressor circuit, a parallel scan path arrangement, and a compactor circuit. The decompressor circuit receives compressed input data from one or more inputs from a tester, decompresses the compressed input data into parallel stimulus patterns that are input to parallel scan paths. The compactor circuit receives parallel response patterns that are output from the parallel scan paths, compacts the response patterns down to one or more compressed data outputs that are input to the tester. A first advantage of TCAs is that they allow a large number of shorter length parallel scan paths to be accessed using only a small number of compressed data inputs and compressed data outputs. A second advantage of TCAs is that they reduce the amount of test data that needs to be transmitted between the tester and device under test, since the test data is compressed. Today device TCAs must be accessed for testing by connecting the device TCA interface directly to a tester. The present disclosure provides methods and apparatuses for allowing a device TCA to be accessed for testing when the device is not connected directly to a tester but rather exists in a serial path containing other devices.
FIG. 1 illustrates an example of device 100 containing a test compression architecture (TCA) 102. The TCA 102 is interfaced to an external tester via a compressed data input lead (CI), a compressed data output lead (CO), a scan clock (SC) input lead, and a scan enable (SE) input lead. While TCAs may have more than one CI input and more than one CO output, this disclosure focuses on TCAs that use a single CI input and a single CO output. The TCA 102 comprises a decompressor 104, a compactor 106, and parallel scan paths 108. The TCA 102 may also include a clock selector (CS) 110 to allow the parallel scan paths to be clocked by the devices functional clock (FC) at times when the parallel scan paths are capturing response data. The decompressor has inputs coupled to the CI, SC and SE inputs and outputs coupled to the scan inputs (SI) of the parallel scan paths 108. The compactor has inputs coupled to the scan outputs (SO) of parallel scan paths 108 and an output coupled to the CO output. The parallel scan paths 108, in addition to the SI inputs and SO outputs, have inputs coupled to the SC and SE inputs, inputs coupled to response outputs from combinational logic, and outputs coupled to stimulus inputs to combinational logic, as shown in FIG. 3. If the CS 110 is used, the SE input will control it to pass the SC signal to the parallel scan paths 108 during shift operations and to pass the FC signal to the parallel scan paths 108 during capture operations.
FIG. 2 illustrates the operational states 202 and 204 of the TCA during test. In state 202 when the SE input is low and an SC input occurs the parallel scan paths capture response data from the combinational logic and the decompressor is reset to a known state. If CS 110 is used, the logic low on SE will select the FC signal to clock the parallel scan paths in state 202. In state 204 when the SE input is high and SC inputs occur the decompressor 104 decompresses the data input on CI into parallel scan inputs (SI) that are shifted into the parallel scan paths, and the compactor 106 inputs and compacts the parallel scan outputs (SO) from the parallel scan paths into a single output which is output on CO. If CS 110 is used, the logic high on SE will select the SC signal to clock the parallel scan paths in state 204. The TCA will remain in state 204 until the compressed input to the parallel scan paths and the compressed output from the scan paths is complete. As can be seen the capture and shift operation states of the TCA is similar to the capture and shift operation states of conventional scan paths, with the exception that the TCA includes the additional operations of decompressing the data input on CI to produce the scan inputs (SI) to the parallel scan paths and compressing the scan outputs (SO) from the parallel scan paths into a compressed form that can be output on CO.
While the example of FIG. 2 shows SE being low in state 202 and high in state 204, the logic levels of SE for these states could be reversed if desire.
Most known decompressors 104 utilize a linear feedback state machine (LFSM) in conjunction with a phase shifter circuit to produce the output patterns that are applied to the SI inputs of the parallel scan paths 108. In the referenced Mentor TestKompress™ technology, the LFSM is referred to as a ring generator which is a particular type of linear feedback shift register. The ring generator receives the CI data and, in response, produces pseudo random input patterns to the phase shifter. The phase shifter responds to the pseudo random input patterns to output stimulus input (SI) patterns to the parallel scan paths. The CI input modifies the output patterns from the ring generator to allow the phase shifter to produce the desired stimulus pattern input to the parallel scan paths.
Most known compactors 106 utilize XOR gating trees that input the scan outputs (SO) from the parallel scan paths and compress them, via XOR gating, into a single compacted signal that can be output on CO. While simple compactors may only use XOR gating trees, more sophisticated compactors, such as the compactor used the reference Mentor TestKompress™ technology, may use XOR gating trees in combination with masking circuitry to allow masking off unknown scan outputs (SO) from the parallel scan path scan to prevent the unknown scan outputs from corrupting the compacted signal output on CO. If the compactor contains masking circuitry it can receive masking data (MD) from the decompressor 104 and control from SC and SE to load the masking data, as shown in dotted line in FIG. 1.
FIG. 4 illustrates an example of a device 402 with a TCA 102 being directly connected to an external tester 404 via the CI, SC, SE and CO TCA interface signals to allow TCA test patterns to be applied to the device. This example is typical of how the device manufacturer would test the device.
FIG. 5 illustrates the tester 404 of FIG. 4 operating the SC and SE signals to perform a TCA scan cycle. The scan cycle includes a capture operation 502 that Captures response data and Resets the decompressor (CR) to a starting seed state, i.e. state 202 of FIG. 2, followed by a shift operation 504, whereby the tester inputs CI data to the TCA decompressor 104 and receives CO data from the TCA compactor, i.e. state 204 of FIG. 2. The shift operation 504 continues until the parallel scan paths are filled with stimulus data and emptied of response data. The scan cycle of FIG. 5 repeats 508 until the TCA test is complete.
FIGS. 4 and 5 have illustrated an example of how a tester 404 can access a device's TCA 102 for testing when a connection can be made between the tester and the device's TCA interface. As seen in FIG. 4 the connection between the tester and device TCA requires a direct connection for the CI signal, a direct connection for the SC signal, a direct connection for the SE signal and a direct connection for the CO signal.
FIG. 6 illustrates an example of a device 602 with a TCA 102 being connected to an external JTAG controller 606 via the device's test access port (TAP) 604. The TAP is a well known device test interface defined in IEEE standard 1149.1. The interface between the JTAG controller 606 and TAP 604 includes test data input (TDI), test clock (TCK), test mode select (TMS), and test data output (TDO) signal leads. The TAP 604 is adapted to interface with the TCA's CI, SC, SE and CO signals. This example allows device manufacturer test patterns to be applied to the device TCA from a JTAG controller.
FIG. 7 illustrates the TAP 604 in more detail and its interface to TCA 102. The TAP 604 includes a TAP controller 702, instruction register (IR) 704, single bit bypass register (BR) 706, boundary scan register (BSR) 708, multiplexer 710, multiplexer 712, and decode circuit 714, all connected as shown. The TAP controller 702 responds to TCK and TMS to shift data through the IR 704, the BR 706, or the BSR 708 from TDI to TDO according to the TAP controller state diagram of FIG. 8. During shift operations, multiplexers 710 and 712 couple the selected register's output to TDO. As seen, the TCA is interfaced to the TAP and operates as an additional data register that can be selected and accessed via TDI and TDO. The instruction shifted into the IR 704 is input to the decode circuit 714 which controls which data register (BR, BSR, or TCA) is selected for access. The decode circuit also receives the TCK and signals from the TAP controller 702 to generate output control signals 716 required to access a selected data register (BR, BSR, or TCA). As seen, when the TCA is selected the decoder circuit 714 provides the SC and SE control signals to the TCA via bus 716.
FIG. 9 illustrates the TAP 604 responding to the JTAG controller 606 to transition through states of FIG. 8 to operate the TCA SC and SE control signals during a TCA scan cycle. In this example, and in response to a TCA select instruction loaded into IR 704, the SC signal is coupled to the Clock-DR signal from the TAP controller 702, via the decode circuit 716, and the SE signal is coupled to the Shift-DR signal from the TAP controller 702, via the decode circuit 716. The Clock-DR and Shift-DR signals are TAP controller signals defined in the IEEE 1149.1 standard used to capture and shift the data register selected by the current instruction in IR 704. The scan cycle includes a capture operation 902 during the Capture-DR state of FIG. 8 that Captures response data and Resets the decompressor (state 202) followed by a shift operation 904 (state 204) during the Shift-DR state of FIG. 8, whereby the JTAG controller 606 inputs CI data to the TCA decompressor 104 and receives CO data from the TCA compactor 106. The shift operation 904 continues until the parallel scan paths are filled with stimulus data and emptied of response data. As seen in FIG. 9, after the shift operation 904 the TAP controller must transition through the Exit1-DR, Update-DR, and Select-DR states 906 of FIG. 8 before returning to the Capture-DR state, so the TCA scan cycle of FIG. 9 is not as efficient time-wise as the TCA scan cycle of FIG. 5. However, the less efficient TCA scan cycle of FIG. 9 is advantageous over the TCA scan cycle of FIG. 5 since the TCA scan cycle of FIG. 9 can be applied at any point in the devices 602 life cycle, i.e. device manufacturing through end product use, since the device TAP signals are dedicated and are always available for access by a JTAG controller. As with TCA scan cycle of FIG. 5, the TCA scan cycle of FIG. 9 repeats 908 until the TCA test is complete.
FIGS. 6 through 9 have illustrated an example of how to adapt a device's TAP 604 to where it can access a device's TCA for testing when a connection can be made between a JTAG controller 606 and the device's TAP 604. As seen in FIG. 6 the connection between the JTAG controller 606 and device TAP 604 requires a direct connection for the TDI signal, a direct connection for the TCK signal, a direct connection for the TMS signal, and a direct connection for the TDO signal to allow the TCA test patterns to be applied to the device during device manufacture.
The present disclosure, as will described in detail below, identifies a problem with using a JTAG controller for applying TCA test patterns to a device when the device exists in a daisy-chain arrangement along with other devices, for example in a customers system. The disclosure provides novel solutions to resolve this TCA test pattern application problem.